The invention relates to a semiconductor component arrangement and a method for fabricating it.
Semiconductor technologies for applications in automotive, consumer or industrial electronics are distinguished by a multiplicity of different types of semiconductor components such as, for example, DMOS-FET (Double Diffused Metal Oxide Semiconductor-Field Effect Transistor) power transistors, MOSFETs, bipolar transistors and also resistors and capacitors. In this case, the components are arranged on a chip usually in regions which are based on a specific functionality. Thus, for instance, a first region may have a DMOS power transistor having a low on resistivity as a low-side switch, high-side switch or in a bridge configuration. A further region may be formed for instance with CMOS logic components for providing flip-flops, digital gates, etc. A further region may likewise be formed with analog components for instance for providing temperature sensors or bandgaps.
Technologies for providing such a multiplicity of semiconductor components are known as BCD (Bipolar CMOS DMOS), SPT (Smart Power Technology) or else SMART technology. Since the semiconductor components of all the regions are formed in a common semiconductor layer, for instance an epitaxial layer, lithographically fabricated semiconductor zones serving for forming semiconductor components are utilized for components of different regions for cost reasons, so that a simultaneous optimization of the semiconductor components in the different regions is required. Such an optimization with regard to the electrical properties at the semiconductor components in the different regions often leads to problems and compromise solutions in practice. However, by way of example, in the case of a CMOS-DMOS technology with a DMOS embodied as a field plate trench transistor, the analog components are realized within voltage-stable semiconductor zones of the p conductivity type. In addition, there are insulated p-channel MOSFETs and vertical bipolar components which are in each case formed in a deeply implanted semiconductor zone of the p conductivity type. In the case of this technology, the thickness of the epitaxial layer is determined by the electrical properties of the analog components and the DMOS transistor, on account of the field plate trench arrangement, has an on average significantly higher breakdown voltage than the semiconductor wells of the p conductivity type for the analog components. It would be desirable for robustness reasons, however, to form the DMOS power transistor with a lower breakdown voltage in comparison with the analog wells of the p conductivity type, so that it can protect them from electrical overloading such as e.g., due to ESD (Electrostatic Discharge) or EOS (Electrical Overstress) and has an optimized on resistance Ron. The same applies in lessened form to a semiconductor technology with DMOS formed in planar fashion.
For these and other reasons, there is a need for the present invention.